The generation of the Local Oscillator (LO) carriers used in radio transceivers is usually done with a phase-locked loop (PLL). With this circuit, an output frequency can only be an integer multiple of a reference frequency (Fout=N×Fref), which implies this reference frequency cannot be higher than the channel spacing. This limits the PLL bandwidth to approximately one tenth of the channel spacing, which implies settling times are sometimes too long.
Also, the required frequency resolution sometimes is just too small to synthesize it as an integer multiple of a reference crystal.
A fractional-N synthesizer does not have a constant value for the PLL division ratio N, but instead it toggles between two or more integer values, resulting in a non-integer average division ratio. Therefore, the reference frequency can be chosen freely and constraints on the loop bandwidth disappear. This toggling however introduces noise, which can be compared to the quantization noise in an Analog-to-Digital converter (ADC).
Therefore, all known fractional-N synthesizers use a sigma-delta modulator to decide on the actual division ratio N. As in a sigma-delta ADC, this modulator shapes the noise introduced by toggling to higher frequencies, where it can be removed by the low-pass filtering action of the PLL loop. For more information on this, see “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”, IEEE Journal of Solid-State Circuits, vol. 28, no. 5, May 1993, pp. 553-559, which is herein incorporated by reference.
Although the loop bandwidth is no longer limited by the small reference frequency, the loop filter must remove the delta-sigma noise that has been shaped away from the low frequencies to the high frequencies. This requires a lot of filtering, generally resulting in a loop bandwidth as small as with an integer-N PLL and with high-order filters. As these filters are too big to be integrated on chip, they are implemented as external components, resulting in higher cost.